View AD7819_2593423.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7819 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 +2.7 v to +5.5 v, 200 ksps 8-bit sampling adc functional block diagram features 8-bit adc with 4.5 m s conversion time on-chip track and hold operating supply range: +2.7 v to +5.5 v specifications at +2.7 v C 3.6 v and 5 v 6 10% 8-bit parallel interface 8-bit read power performance normal operation 10.5 mw, v dd = 3 v automatic power-down 57.75 m w @ 1 ksps, v dd = 3 v analog input range: 0 v to v ref reference input range: 1.2 v to v dd general description the AD7819 is a high speed, microprocessor-compatible, 8-bit analog-to-digi tal converter with a maximum throughput of 200 ksps. the converter operates off a single +2.7 v to +5.5 v supply and contains a 4.5 m s successive approximation a/d converter, track/hold circuitry, on-chip clock oscillator and 8-bit wide parallel interface. the parallel interface is designed to allow easy interfacing to microprocessors and dsps. using only address decoding logic the AD7819 is easily mapped into the microprocessor address space. when used in its power-down mode, the AD7819 automatically powers down at the end of a conversion and powers up at the start of a new conversion. this feature significantly reduces the power consumption of the part at lower throughput rates. the AD7819 can also operate in a high speed mode where the part is not powered down between conversions. in this mode of opera- tion the part is capable of providing 200 ksps throughput. the part is available in a small, 16-pin 0.3" wide, plastic dual- in-line package (dip); in a 16-pin, 0.15" wide, narrow body small outline ic (soic) and in a 16-p in, narrow body, thin shrink small outline package (tssop). product highlights 1. low power, single supply operation the AD7819 operates from a single +2.7 v to +5.5 v sup- ply and typically consumes only 10.5 mw of power. the power dissipation can be significantly reduced at lower throughput rates by using the automatic power-down mode. 2. automatic power-down the automatic power-down mode, whereby the AD7819 goes into power-down mode at the end of a conversion and powers up before the next conversion, means the AD7819 is ideal for battery powered applications; e.g., 57.75 m w @ 1 ksps. (see power vs. throughput rate section.) 3. parallel interface an easy to use 8-bit wide parallel interface allows interfacing to most popular microprocessors and dsps with minimal external circuitry. 4. dynamic specifications for dsp users in addition to the traditional adc specifications, the AD7819 is specified for ac parameters, including signal-to-noise ratio and distortion. clock osc charge redistribution dac three- state drivers control logic busy cs rd convst v in v dd agnd v ref db7 db0 comp t/h AD7819
C2C rev. 0 AD7819Cspecifications 1 (gnd = 0 v, v ref = +v dd = 3 v 6 10% to 5 v 6 10%). all specifications C40 8 c to +125 8 c unless otherwise noted.) parameter y version units test conditions/comments dynamic performance f in = 30 khz, f sample = 136 khz signal to (noise + distortion) ratio 1 48 db min total harmonic distortion (thd) 1 C70 db typ peak harmonic or spurious noise 1 C70 db typ intermodulation distortion 2 fa = 29.1 khz; fb = 29.8 khz 2nd order terms C77 db typ 3rd order terms C77 db typ dc accuracy resolution 8 bits minimum resolution for which no missing codes are guaranteed 8 bits relative accuracy 1 0.5 lsb max differential nonlinearity (dnl) 1 0.5 lsb max total unadjusted error 1 1 lsb max gain error 1 0.5 lsb max offset error 1 0.5 lsb max analog input input voltage range 0 v min v ref v max input leakage current 2 1 m a max input capacitance 2 15 pf mx reference inputs 2 v ref input voltage range 1.2 v min v dd v max input leakage current 1 m a max input capacitance 20 pf max logic inputs 2 v inh, input high voltage 2.0 v min v inl, input low voltage 0.4 v max (0.8 v max, v dd = 5 v) input current, i in 1 m a max typically 10 na, v in = 0 v to v dd input capacitance, c in 8 pf max logic outputs output high voltage, v oh 2.4 v min i source = 200 m a output low voltage, v ol 0.4 v max i sink = 200 m a high impedance leakage current 1 m a max high impedance capacitance 15 pf max conversion rate conversion time 4.5 m s max track/hold acquisition time 1 100 ns max see dc acquisition section power supply v dd 2.7C5.5 volts for specified performance i dd digital inputs = 0 v or v dd normal operation 3.5 ma max power-down 1 m a max v dd = 5 v power dissipation normal operation 17.5 mw max v dd = 5 v power-down 5 m w max auto power-down (mode 2) v dd = 3 v 1 ksps throughput 57.75 m w max 10 ksps throughput 577.5 m w max 50 ksps throughput 2.89 mw max notes 1 see terminology section. 2 sample tested during initial release and after any redesign or process change that may affect this parameter. specifications subject to change without notice.
AD7819 C3C rev. 0 timing characteristics 1, 2 parameter v dd = 3 v 6 10% v dd = 5 v 6 10% units conditions/comments t power-up 11 m s (max) power-up time of AD7819 after rising edge of convst . t 1 4.5 4.5 m s (max) conversion time. t 2 30 30 ns (min) convst pulse width. t 3 30 30 ns (max) convst falling edge to busy rising edge delay. t 4 0 0 ns (min) cs to rd setup time. t 5 0 0 ns (min) cs hold time after rd high. t 6 3 10 10 ns (max) data access time after rd low. t 7 3, 4 10 10 ns (max) bus relinquish time after rd high. t 8 3 50 50 ns (min) data bus relinquish to falling edge of convst delay. notes 1 sample tested to ensure compliance. 2 see figures 12, 13 and 14. 3 these numbers are measured with the load circuit of figure 1. they are defined as the time required for the o/p to cross 0.8 v or 2.4 v for v dd = 5 v 10% and 0.4 v or 2 v for v dd = 3 v 10%. 4 derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 7 , quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. (C40 8 c to +125 8 c, unless otherwise noted) absolute maximum ratings* v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v digital input voltage to dgnd ( convst , rd , cs ) . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v digital output voltage to dgnd (busy, db0Cdb7) . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v ref in to agnd . . . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v analog input . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c plastic dip package, power dissipation . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . +105 c/w lead temperature, (soldering 10 sec) . . . . . . . . . . . +260 c soic package, power dissipation . . . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c ssop package, power dissipation . . . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 115 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kv *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. +1.6v 200? i ol 200? i oh c l 50pf to output pin figure 1. load circuit for digital output timing specifications ordering guide linearity error package package model (lsb) description option AD7819yn 1 lsb plastic dip n-16 AD7819yr 1 lsb small outline ic r-16a AD7819yru 1 lsb thin shrink small outline ru-16 (tssop)
AD7819 C4C rev. 0 pin function descriptions pin no. mnemonic description 1v ref reference input, 1.2 v to v dd . 2v in analog input, 0 v to v ref . 3 gnd analog and digital ground. 4 convst convert start. a low-to-high transition on this pin initiates a 1 m s pulse on an internally generated convst signal. a high-to-low transition on this line initiates the conversion process if the internal convst signal is low. depending on the signal on this pin at the end of a conversion, the AD7819 automatically powers down. 5 cs chip select. this is a logic input. cs is used in conjunction with rd to enable outputs. 6 rd read pin. this is a logic input. when cs is low and rd goes low, the db7Cdb0 leave their high impedance state and data is driven onto the data bus. 7 busy adc busy signal. this is a logic output. this signal goes logic high during the conversion process. 8C15 db0Cdb7 data bit 0 to 7. these outputs are three-state ttl-compatible. 16 v dd positive power supply voltage, +2.7 v to +5.5 v. pin configuration dip/soic 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD7819 v ref db5 db6 db7 v dd v in gnd convst db2 db3 db4 cs rd busy db0 db1
AD7819 C5C rev. 0 terminology signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quan- tization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to (noise + distortion) = (6.02 n + 1.76) db thus for an 8-bit converter, this is 50 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the AD7819 it is defined as: thd ( db ) = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the AD7819 is tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second and third order terms are of differ- ent significance. the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified sepa- rately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dbs. relative accuracy relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., agnd + 1 lsb. offset error match this is the difference in offset error between any two channels. gain error this is the deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) from the ideal, i.e., vref C 1 lsb, after the offset error has been adjusted out. gain error match this is the difference in gain error between any two channels. track/hold acquisition time track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion (the point at which the track/hold returns to track mode). it also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected v in input of the AD7819. it means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a step input change to v in before starting another conversion, to ensure that the part operates to specification.
AD7819 C6C rev. 0 circuit description converter operation the AD7819 is a successive approximation analog-to-digital converter based around a charge redistribution dac. the adc can convert analog input signals in the range 0 v to v dd . fig- ures 2 and 3 below show simplified schematics of the adc. figure 2 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition and the sampling capacitor acquires the signal on v in+ . charge restribution dac control logic clock osc comparator sw2 v dd /3 acquisition phase sampling capacitor sw1 a b agnd v in figure 2. adc track phase when the adc starts a conversion, see figure 3, sw2 will open and sw1 will move to position b causing the comparator to become unbalanced. the control logic and the charge redis- tribution dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebal- anced the conversion is complete. the control logic generates the adc output code. figure 7 shows the adc transfer function. charge restribution dac control logic clock osc comparator sw2 v dd /3 conversion phase sampling capacitor sw1 a b agnd v in figure 3. adc conversion phase typical connection diagram figure 4 shows a typical connection diagram for the AD7819. the parallel interface is implemented using an 8-bit data bus, the falling edge of convst brings the busy signal high and at the end of conversion, the falling edge of busy is used to initiate an isr on a microprocessor. (see parallel interface section for more details.) v ref is connected to a well decoupled v dd pin to provide an analog input range of 0 v to v dd . when v dd is first connected the AD7819 powers up in a low current mode, i.e., power down. a rising edge on the convst input will cause the part to power up. (see power-up times section.) if power consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power performance. see power vs. throughput rate section of the data sheet. busy rd cs convst db0-db7 v dd v ref v in gnd AD7819 m c/ m p parallel interface 0v to v ref input 0.1 m f 10 m f supply +2.7v to +5.5v figure 4. typical connection diagram analog input figure 5 shows an equivalent circuit of the analog input struc- ture of the AD7819. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mv. this will cause these diodes to become forward biased and start conducting current into the substrate. 20 ma is the maximum current these diodes can conduct with- out causing irreversible damage to the part. the capacitor c2 is typically about 4 pf and can be primarily attributed to pin capacitance. the resistor r1 is a lumped component made up of the on resistance of a multiplexer and a switch. this resistor is typically about 125 w . the capacitor c1 is the adc sampling capacitor and has a capacitance of 3.5 pf. v dd v in c2 4pf d1 d2 r1 125 w c1 3.5pf v dd /3 convert phase ?switch open track phase ?switch closed figure 5. equivalent analog input circuit dc acquisition time the adc starts a new acquisition phase at the end of a conver- sion and ends on the falling edge of the convst signal. at the end of a conversion there is a settling time associated with the sampling circuit. this settling time lasts approximately 100 ns. the analog signal on v in is also being acquired during this set- tling time. the minimum acquisition time needed is approxi- mately 100 ns. figure 6 shows the equivalent charging circuit for the sampling capacitor when the adc is in its acquisition phase. r2 represents the source impedance of a buffer amplifier or resistive network, r1 is an internal multiplexer resistance and c1 is the sampling capacitor. v in r1 125 w r2 c1 3.5pf figure 6. equivalent sampling circuit
AD7819 C7C rev. 0 during the acquisition phase the sampling capacitor must be charged to within a 1/2 lsb of its final value. the time it takes to charge the sampling capacitor (t charge ) is given by the following formula: t charge = 6.2 ( r 2 + 125 w ) 3.5 pf for small values of source impedance, the settling time associ- ated with the sampling circuit (100 ns) is, in effect, the acquisi- tion time of the adc. for example, with a source impedance (r2) of 10 w , the charge time for the sampling capacitor is approximately 3 ns. the charge time becomes significant for source impedances of 2 k w and greater. ac acquisition time in ac applications it is recommended to always buffer analog input signals. the source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of the adc. large values of source impedance will cause the thd to degrade at high throughput rates. adc transfer function the output coding of the AD7819 is straight binary. the de- signed code transitions occur at successive integer lsb values (i.e., 1 lsb, 2 lsbs, etc.). the lsb size is = v ref /256. the ideal transfer characteristic for the AD7819 is shown in figure 7 below. 111...111 111...110 111...000 011...111 000...010 000...001 000...000 adc code 1lsb = v ref /256 0v 1lsb +v ref ?lsb analog input figure 7. transfer characteristic power-up times the AD7819 has a 1 m s power-up time. when v dd is first con- nected, the AD7819 is in a low current mode of operation. in order to carry out a conversion the AD7819 must first be pow- ered up. the adc is powered up by a rising edge on an inter- nally generated convst signal, which occurs as a result of a rising edge on the external convst pin. the rising edge of the external convst signal initiates a 1 m s pulse on the internal convst signal. this pulse is present to ensure the part has enough time to power-up before a conversion is initiated, as a conversion is initiated on the falling edge of gated convst . see timing and control section. care must be taken to ensure that the convst pin of the AD7819 is logic low when v dd is first applied. when operating in mode 2, the adc is powered down at the end of each conversion and powered up again before the next conversion is initiated. (see figure 8.) t power-up 1 s t power-up 1 s t power-up 1 s mode 1 mode 2 v dd ext int v dd ext int figure 8. power-up times power vs. throughput rate by operating the AD7819 in mode 2, the average power con- sumption of the AD7819 decreases at lower throughput rates. figure 9 shows how the a utomatic power-down is implemented using the external convst signal to achieve the optimum power performance for the AD7819. the AD7819 is operated in mode 2 and the duration of the external convst pulse is set to be equal to or less than the power-up time of the device. as the throughput rate is reduced, the device remains in its power- down state longer and the average power consumption over time drops accordingly. ext int power-down t power-up 1 s t convert 5.0 s t cycle 100 s @ 10ksps figure 9. automatic power-down if, for example, the AD7819 is operated in a continuous sam- pling mode with a throughput rate of 10 ksps, the power con- sumption is calculated as follows. the power dissipation during normal operation is 10.5 mw, v dd = 3 v. if the power-up time is 1 m s and the conversion time is 4.5 m s, the AD7819 can be said to dissipate 10.5 mw for 5.5 m s (worst case) during each conversion cycle. if the throughput rate is 10 ksps, the cycle time is then 100 m s and the average power dissipated during each cycle is (5.5/100) (10.5 mw) = 577.5 m w.
AD7819 C8C rev. 0 typical performance characteristics throughput ?ksps power ?mw 10 1 0.01 050 5 1015202530354045 0.1 figure 10. power vs. throughput 0 ?0 ?00 dbs ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 frequency ?khz 066 7 1320273340475360 AD7819 2048 point fft sampling 136.054khz fin 29.961khz figure 11. snr timing and control the AD7819 has only one input for timing and control, i.e., the convst (convert start signal). the rising edge of this convst signal initiates a 1 m s pulse on an internally generated convst signal. this pulse is present to ensure the part has enough time to power up before a conversion is initiated. if the external convst signal is low, the falling edge of the inter- nal convst signal will cause the sampling circuit to go into hold mode and initiate a conversion. if, however, the external convst signal is high when the internal convst goes low, it is upon the falling edge of the external convst signal that the sampling circuitry will go into hold mode and initiate a conversion. the use of the internally generated 1 m s pulse as previously described can be likened to the configuration shown in figure 12. the application of a convst signal at the convst pin triggers the generation of a 1 m s pulse. both the external convst and this internal convst are input to an or gate. the resultant signal has the duration of the longer of the two input signals. once a conversion has been initiated, the busy signal goes high to indicate a conversion is in progress. at the end of conversion the sampling circuit returns to its t rack- ing mode. the end of conversion is indicated by the busy signal going low. this signal may be used to initiate an isr on a microprocessor. at this point the conversion result is latched into the output register where it may be read. the AD7819 has an 8-bit wide parallel interface. the state of the external convst signal at the end of conversion also establishes the mode of operation of the AD7819. mode 1 operation (high speed sampling) if the external convst is logic high when busy goes low, the part is said to be in mode 1 operation. while operating in mode 1 the AD7819 will not power down between conversi ons. the AD7819 should be operated in mode 1 for high speed sam pling applications, i.e., throughputs greater than 100 ksps. figure 13 shows the timing for mode 1 operation. from this diagram one can see that a minimum delay of the sum of the conversion time and read time must be left between two successive falling edges of the external convst . this is to ensure that a conversion is not initiated during a read. mode 2 operation (automatic power-down) at slower throughput rates the AD7819 may be powered down between conversion to give a superior power performance. this is mode 2 operation and it is achieved by bringing the convst signal logic low before the falling edge of busy. figure 14 shows the timing for mode 2 operation. the falling edge of the external convst signal may occur before or after the falling edge of the internal convst signal, but it is the later occurring falling edge of both that controls when the first conversion will take place. if the falling edge of the external convst occurs after that of the internal convst , it means that the moment of the first conversion is controlled exactly, regardless of any jitter associated with the internal convst signal. the parallel interface is still fully operational while the AD7819 is powered down. the AD7819 is powered up again on the rising edge of the convst signal. the gated convst pulse will now remain high long enough for the AD7819 to fully power up, which takes about 1 m s. this is ensured by the internal convst signal, which will remain high for 1 m s. 1 s ext int (pin 4) gated figure 12.
AD7819 C9C rev. 0 parallel interface the parallel interface of the AD7819 is eight bits wide. the output data buffers are activated when both cs and rd are logic low. at this point the contents of the data register are placed on the 8 -bit data bus. figure 15 shows the timing diagram for the parallel port. the parallel inte rface of the AD7819 is reset 8 msbs t 1 t 2 t 3 t power-up ext convst int convst busy cs / rd db7?b0 figure 13. mode 1 operation 8 msbs t 1 t 3 ext convst int convst busy cs / rd db7?b0 t power-up figure 14. mode 2 operation when busy goes logic high. care must be taken to ensure that a read operation d oes not occur while busy is high. data read from the AD7819 while busy is high will be invalid. for optimum performance the read operation should end at least 100 ns (t 10 ) prior to the falling edge of the next convst . 8 msbs convst busy cs db7?b0 t 2 t 3 t 1 t 4 t 6 t 7 t 5 t 8 rd figure 15. parallel port timing
AD7819 C10C rev. 0 microprocessor interfacing the parallel port on the AD7819 allows the device to be inter- faced to a range of many different microcontrollers. this section explains how to interface the AD7819 with some of the more common microcontroller parallel interface protocols. AD7819 to 8051 figure 16 shows a parallel interface between the AD7819 and the 8051 microcontroller. the busy signal on the AD7819 pro- vides an interrupt request to the 8051 when a conversion begins. port 0 of the 8051 may serve as an input or output port, or as in this case when used together, may be used as a bidirectional low-order address and data bus. the address latch enable out- put of the 8051 is used to latch the low byte of the address dur- ing accesses to the device, while the high-order address byte is supplied from port 2. port 2 latches remain stable when the AD7819 is addressed, as they do not have to be turned around (set to 1) for data input as is the case for port 0. AD7819 * 8051* ad0?d7 ale a8?15 rd int latch decoder db0?b7 cs rd busy * additional pins omitted for clarity figure 16. interfacing to the 8051 AD7819 to pic16c6x/7x figure 17 shows a parallel interface between the AD7819 and the pic16c64/65/74. the busy signal on the AD7819 provides an interrupt request to the microcontroller when a conversion be- gins. of the pic16c6x/7x range of microcontrollers, only the pic16c64/65/74 can provide the option of a parallel slave port. port d of the microcontroller will operate as an 8-bit wide parallel slave port when control bit pspmode in the trise register is set. setting pspmode enables the port pin re0 to be the rd output and re2 to be the cs output. for this functionality, the corresponding data direction bits of the trise register must be configured as outputs (reset to 0). see user pic16/17 microcontroller user manual. pic16c6x/7x* psp0?sp7 rd int * additional pins omitted for clarity cs AD7819 * db0?b7 cs rd busy figure 17. interfacing to the pic16c6x/7x AD7819 to adsp-21xx figure 18 shows a parallel interface between the AD7819 and the adsp-21xx series of dsps. as before, the busy signal on the AD7819 provides an interrupt request to the dsp when a conversion begins. * additional pins omitted for clarity address decode logic en AD7819 * db0?b7 cs rd busy adsp-21xx* d0?7 dms a13?0 rd irq figure 18. interfacing to the adsp-21xx
AD7819 C11C rev. 0 outline dimensions dimensions shown in inches and (mm). 16-lead plastic dip (n-16) 16 18 9 0.840 (21.33) 0.745 (18.93) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-lead small outline package (r-16a) 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 16-lead thin shrink small outline package (ru-16) 16 9 8 1 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0
C12C c3059C12C6/97 printed in u.s.a.

▲Up To Search▲

Price & Availability of AD7819

	To Download AD7819 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .